74S374 ( SN74S374N )
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Kategori
Dorukan Stok No
DRK-1170-14
Fiyat
0,20 USD + KDV
Havale
7,50 TL
(%3,00 havale indirimi)
7,73 TL
74S Serisi
74S374 - Octal D-Type Transparent Latches and
Edge-Triggered Flip-Flops
74S374 - Octal D-Type Transparent Latches and
Edge-Triggered Flip-Flops
These 8-bit registers feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads.
The high-impedance 3-state and increased
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
The eight flip-flops of the ’LS374 and ’S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
designed specifically for driving highly capacitive
or relatively low-impedance loads.
The high-impedance 3-state and increased
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
The eight flip-flops of the ’LS374 and ’S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
Features
• Choice of Eight Latches or Eight D-Type
Flip-Flops in a Single Package
• 3-State Bus-Driving Outputs
• Full Parallel Access for Loading
• Buffered Control Inputs
• Clock-Enable Input Has Hysteresis to
Improve Noise Rejection (’S373 and ’S374)
• P-N-P Inputs Reduce DC Loading on Data
Lines (’S373 and ’S374)
Operating temp. range : 0°C - 70°C
Vcc range : 4,75V - 5,25V
Package : DIP20
• Choice of Eight Latches or Eight D-Type
Flip-Flops in a Single Package
• 3-State Bus-Driving Outputs
• Full Parallel Access for Loading
• Buffered Control Inputs
• Clock-Enable Input Has Hysteresis to
Improve Noise Rejection (’S373 and ’S374)
• P-N-P Inputs Reduce DC Loading on Data
Lines (’S373 and ’S374)
Operating temp. range : 0°C - 70°C
Vcc range : 4,75V - 5,25V
Package : DIP20
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